Active Leakage Control with Sleep Transistors and Body Bias

Leakage power accounts for an increasingly larger portion of total power consumption in deep submicron technologies. Active leakage control method reduces leakage power by dynamically disconnecting supply to inactive blocks and adjusting body bias to further limit leakage and maintain performance. The active leakage control scheme is advantageous for blocks with low activity factors and relatively long idle periods. A clock distribution tree, an 8-bit carry look-ahead adder, an 8-bit address decoder, and a SRAM cell were simulated in SPICE using BPTM 45nm, 65nm, 100nm, and 180nm technology models.